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features ? high-performance, low-power 32-bit atmel ? avr ? microcontroller ? compact single-cycle risc instruction set including dsp instructions ? read-modify-write instructions and atomic bit manipulation ? performance ? up to 64dmips running at 50mhz from flash (1 flash wait state) ? up to 36dmips running at 25mhz from flash (0 flash wait state) ? memory protection unit (mpu) ? secure access unit (sau) providing user-defined peripheral protection ? picopower ? technology for ultra-low power consumption ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? 12 peripheral dma channels improve speed for peripheral communication ? internal high -speed flash ? 256kbytes, 128kbytes, and 64kbytes versions ? single-cycle access up to 25mhz ? flashvault technology allows pre-programmed secure library support for end user applications ? prefetch buffer optimizing instru ction execution at maximum speed ? 100,000 write cycles, 15-year data retention capability ? flash security locks and us er-defined configuration area ? internal high-speed sram, si ngle-cycle access at full speed ? 32kbytes (256kbytes and 128kbytes flash) and 16kbytes (64kbytes flash) ? interrupt controller (intc) ? autovectored low-latency interrupt service with programmable priority ? external interrupt controller (eic) ? peripheral event system for direct pe ripheral to periph eral communication ? system functions ? power and clock manager ? sleepwalking power saving control ? internal system rc oscillator (rcsys) ? 32 khz oscillator ? multipurpose oscillator, phase locked loop (pll), and digital frequency locked loop (dfll) ? windowed watchdog timer (wdt) ? asynchronous timer (ast) with real-time clock capability ? counter or calendar mode supported ? frequency meter (freqm) for accurate measuring of clock frequency ? universal serial bus (usbc) ? full speed and low speed usb device support ? multi-packet ping-pong mode ? six 16-bit timer/co unter (tc) channels ? external clock inputs, pwm, capture, and various counting capabilities ? 36 pwm channels (pwma) ? 12-bit pwm with a source clock up to 150mhz ? four universal synchronous/asynchro nous receiver/transmitters (usart) ? independent baudrate generator, support for spi ? support for hardware handshaking 32142ds?06/2013 32-bit atmel avr microcontroller atuc256l3u atuc128l3u atuc64l3u atuc256l4u atuc128l4u atuc64l4u summary
2 32142ds?06/2013 atuc64/128/256l3/4u ? one master/slave serial peripheral inte rface (spi) with ch ip select signals ? up to 15 spi slaves can be addressed ? two master and two slave two-wire interfaces (twi), 400kbit/s i 2 c-compatible ? one 8-channel analog-to -digital converter (adc) with up to 12 bits resolution ? internal temperature sensor ? eight analog comparators (ac) with optional window detection ? capacitive touch (cat) module ? hardware-assisted atmel ? avr ? qtouch ? and atmel ? avr ? qmatrix touch acquisition ? supports qtouch and qmatrix capture from capacitive touch sensors ? qtouch library support ? capacitive touch buttons, sliders, and wheels ? qtouch and qmatrix acquisition ? audio bitstream dac (abdacb) suitable for stereo audio ? inter-ic sound (iisc) controller ? compliant with inter-ic sound (i 2 s) specification ? on-chip non-intrusive debug system ? nexus class 2+, runtime control, non-intrusive data and program trace ? awire single-pin programming trace and debug interface, muxed with reset pin ? nanotrace provides trace capabilities through jtag or awire interface ? 64-pin tqfp/qfn (51 gpio pins), 48-pin tqfp/qfn/tllga (36 gpio pins) ? six high-drive i/o pins (64-pin packages), four high-drive i/o pins (48-pin packages) ? single 1.62-3.6v power supply
3 32142ds?06/2013 atuc64/128/256l3/4u 1. description the atmel ? avr ? atuc64/128/256l3/4u is a complete system-on-chip microcontroller based on the avr32 uc risc processor running at frequencies up to 50mhz. avr32 uc is a high- performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applica- tions, with particular emphasis on low pow er consumption, high code density, and high performance. the processor implements a memory protection unit (mpu) and a fast and flexible interrupt con- troller for supporting m odern and real-tim e operating systems. the se cure access unit (sau) is used together with the mpu to provide the required security and integrity. higher computation capability is achieved using a rich set of dsp instructions. the atuc64/128/256l3/4u embeds state-of-the-art picopower technology for ultra-low power consumption. combined power control techniques are used to bring active current consumption down to 174a/mhz, and leakage down to 220na while still retaining a bank of backup regis- ters. the device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumptio n with the feature set required for the application. the peripheral direct memory access (dma) controller enables data transfers between periph- erals and memories without processor involvement. the peripheral dma controller drastically reduces processing overhead when transferring continuous and large data streams. the atuc64/128/256l3/4u incorporates on-chip flash and sram memories for secure and fast access. the flashvault technology allows secure libraries to be programmed into the device. the secure libraries can be executed while the cpu is in secure state, but not read by non-secure software in the device. the device can thus be shipped to end customers, who will be able to program their own code into the device to access the secure libraries, but without risk of compromising the proprietary secure code. the external interrupt controller (eic) allows pins to be configured as external interrupts. each external interrupt has its own interrupt request and can be individually masked. the peripheral event system allows peripherals to receive, react to, and send peripheral events without cpu intervention. asynchronous interrupts allow advanced peripheral operation in low power sleep modes. the power manager (pm) improves design flexibility and securi ty. the power ma nager supports sleepwalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. power monitoring is supported by on-chip power-on reset (por), brown-out detector (bod), and supply monitor (sm). the device features several oscillators, such as phase locked loop (pll), digital frequency locked loop (dfll), oscillator 0 (osc0), and syst em rc oscillator (rcsys). either of these oscillators can be used as source for the system clock. the dfll is a programmable internal oscillator from 20 to 150mh z. it can be tuned to a high accura cy if an accurate reference clock is running, e.g. the 32khz crystal oscillator. the watchdog timer (wdt) will reset the device unless it is periodically serviced by the soft- ware. this allows the device to recover from a condition that has caused the system to be unstable. the asynchronous timer (ast) combined with th e 32khz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeou t of up to 136 years. the ast can operate in counter or calendar mode.
4 32142ds?06/2013 atuc64/128/256l3/4u the frequency meter (freqm) allows accurate measuring of a clock frequency by comparing it to a known reference clock. the full-speed usb 2.0 device interface (usbc) supports several usb classes at the same time, thanks to the rich end-point configuration. the device includes six identical 16-bit timer/counter (tc) channels. each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. the pulse width modulation controller (pwma) provides 12-bit pwm channels which can be synchronized and controlled from a common timer. 36 pwm channels are available, enabling applications that requir e multiple pwm outputs, such as l cd backlight contro l. the pwm chan- nels can operate independently, with dut y cycles set individually, or in interlinked mode, with multiple channels changed at the same time. the atuc64/128/256l3/4u also features many communication interfaces, like usart, spi, and twi, for communication intensive applicati ons. the usart supports different communica- tion modes, like spi mode and lin mode. a general purpose 8-channel adc is provided, as well as eight analog comparators (ac). the adc can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. the adc also provides an internal temperature sensor input channel. the analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. the capacitive touch (cat) module senses touch on external capacitive touch sensors, using the qtouch technology. capacitive touch sensor s use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. the cat module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. all touch sensors can be configured to oper ate autonomously without software interaction, allowing wakeup from sleep modes when activated. atmel offers the qtouch library for embedding capacitive touch buttons, sliders, and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys as well as adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop, and debug your own touch applications. the audio bitstream dac (abdacb) converts a 16- bit sample value to a digital bitstream with an average value proportional to the sample value. two channels are supported, making the abdac particularly suitable for stereo audio. the inter-ic sound controller (iis c) provides a 5-bit wide, bidi rectional, synchronous, digital audio link with external audio devices. the controll er is compliant with the inter-ic sound (i2s) bus specification. the atuc64/128/256l3/4u integrates a class 2+ nexus 2.0 on-chip debug (ocd) system, with non-intrusive real-time trace and full-speed read/write memory acce ss, in addition to basic runtime control. the nanotrace interface enables trace feature for awire- or jtag-based debuggers. the single-pin awire interface allows all features available through the jtag inter- face to be accessed through the reset pin, a llowing the jtag pins to be used for gpio or peripherals.
5 32142ds?06/2013 atuc64/128/256l3/4u 2. overview 2.1 block diagram figure 2-1. block diagram interrupt controller asynchronous timer peripheral dma controller hsb-pb bridge b hsb-pb bridge a s mm m s s m external interrupt controller high speed bus matrix generalpurpose i/os general purpose i/os pa pb extint[5..1] nmi pa pb spi dma miso, mosi npcs[3..0] usart0 usart1 usart2 usart3 dma rxd txd clk rts, cts watchdog timer sck jtag interface mcko mdo[5..0] mseo[1..0] evti_n tdo tdi tms configuration registers bus 256/128/64 kb flash s flash controller evto_n avr32uc cpu nexus class 2+ ocd instr interface data interface memory interface local bus 32/16 kb sram memory protection unit local bus interface frequency meter pwm controller pwma[35..0] twi master 0 twi master 1 dma twi slave 0 twi slave 1 dma 8-channel adc interface dma power manager reset controller sleep controller clock controller tck awire reset_n capacitive touch module dma ac interface acrefn acan[3..0] acbn[3..0] acbp[3..0] acap[3..0] twck twd twalm twck twd twalm glue logic controller in[7..0] out[1..0] usb 2.0 interface 8ep dma inter-ic sound controller timer/counter 0 timer/counter 1 a[2..0] b [ 2 . . 0 ] audio bitstream dac dma dac0, dac1 dacn0, dacn1 isck iws isdi isdo imck clk sau s/m s d m d p system control interface gclk[9..0] xin32 xout32 osc32k rcsys x i n 0 x o u t 0 osc0 dfll rc32k rc120m rc32out pll gclk_in[2..0] csb[16:0] smp csa[16:0] sync vdiven dis trigger adp[1..0] ad[8..0] dataout advrefp clk[2..0]
6 32142ds?06/2013 atuc64/128/256l3/4u 2.2 configuration summary table 2-1. configuration summary feature atuc256l3u atuc128l3u atuc64l 3u atuc256l4u atuc128l4u atuc64l4u flash 256kb 128kb 64kb 256kb 128kb 64kb sram 32kb 16kb 32kb 16kb gpio 51 36 high-drive pins 6 4 external interrupts 6 twi 2 usart 4 peripheral dma channels 12 peripheral event system 1 spi 1 asynchronous timers 1 timer/counter channels 6 pwm channels 36 frequency meter 1 watchdog timer 1 power manager 1 secure access unit 1 glue logic controller 1 oscillators digital frequency locked loop 20-150mhz (dfll) phase locked loop 40-240mhz (pll) crystal oscillator 0.45-16mhz (osc0) crystal oscillator 32khz (osc32k) rc oscillator 120mhz (rc120m) rc oscillator 115khz (rcsys) rc oscillator 32khz (rc32k) adc 8-channel 12-bit temperature sensor 1 analog comparators 8 capacitive touch module 1 jtag 1 awire 1 usb 1 audio bitstream dac 1 0 iis controller 1 0 max frequency 50mhz packages tqfp64/qfn64 tqfp48/qfn48/tllga48
7 32142ds?06/2013 atuc64/128/256l3/4u 3. package and pinout 3.1 package the device pins are multiplexed with pe ripheral functions as described in section . figure 3-1. atuc64/128/256l4u tqfp48/qfn48 pinout gnd 1 pa09 2 pa08 3 pa03 4 pb12 5 pb00 6 pb02 7 pb03 8 pa22 9 pa06 10 pa00 11 pa05 12 pa02 13 pa01 14 pb13 15 pb14 16 vddin 17 vddcore 18 gnd 19 pb05 20 pb04 21 reset_n 22 pb10 23 pa21 24 pa14 36 vddana 35 advrefp 34 gndana 33 pb08 32 pb07 31 pb06 30 pb09 29 pa04 28 pa11 27 pa13 26 pa20 25 pa15 37 pa16 38 pa17 39 pa19 40 pa18 41 vddio 42 gnd 43 pb11 44 gnd 45 pa10 46 pa12 47 vddio 48
8 32142ds?06/2013 atuc64/128/256l3/4u figure 3-2. atuc64/128/256l4u tllga48 pinout gnd 1 pa09 2 pa08 3 pa03 4 pb12 5 pb00 6 pb02 7 pb03 8 pa22 9 pa06 10 pa00 11 pa05 12 pa02 13 pa01 14 pb13 15 pb14 16 vddin 17 vddcore 18 gnd 19 pb05 20 pb04 21 reset_n 22 pb10 23 pa21 24 pa14 36 vddana 35 advrefp 34 gndana 33 pb08 32 pb07 31 pb06 30 pb09 29 pa04 28 pa11 27 pa13 26 pa20 25 pa15 37 pa16 38 pa17 39 pa19 40 pa18 41 vddio 42 gnd 43 pb11 44 gnd 45 pa10 46 pa12 47 vddio 48
9 32142ds?06/2013 atuc64/128/256l3/4u figure 3-3. atuc64/128/256l3u tqfp64/qfn64 pinout gnd 1 pa09 2 pa08 3 pb19 4 pb20 5 pa03 6 pb12 7 pb00 8 pb02 9 pb03 10 vddio 11 gnd 12 pa22 13 pa06 14 pa00 15 pa05 16 pa02 17 pa01 18 pa07 19 pb01 20 pb26 21 pb13 22 pb14 23 pb27 24 pb08 44 pb07 43 pb06 42 pb22 41 pb21 40 pb09 39 pa04 38 vddio 37 gnd 36 pa11 35 pa13 34 pa20 33 pa15 49 pa16 50 pa17 51 pa19 52 pa18 53 pb23 54 pb24 55 pb11 56 pb15 57 pb16 58 pb17 59 pb18 60 vddin 25 26 gnd 27 pb05 28 pb04 29 30 pb10 31 pa21 32 pa14 48 vddana 47 advrefp 46 gndana 45 pb25 61 pa10 62 pa12 63 vddio 64 vddcore reset_n
10 32142ds?06/2013 atuc64/128/256l3/4u peripheral multiplexing on i/o lines 3.1.1 multiplexed signals each gpio line can be assigned to one of the peripheral functions. the following table describes the peripheral signals multiplexed to the gpio lines. table 3-1. gpio controller func tion multiplexing 48- pin 64- pin pin name g pi o supply pad type gpio function abcde f gh 11 15 pa00 0 vddio normal i/o usart0- txd usart1- rts spi- npcs[2] pwma- pwma[0] scif- gclk[0] cat- csa[2] 14 18 pa01 1 vddio normal i/o usart0- rxd usart1- cts spi- npcs[3] usart1- clk pwma- pwma[1] acifb- acap[0] twims0- twalm cat- csa[1] 13 17 pa02 2 vddio high- drive i/o usart0- rts adcifb- trigger usart2- txd tc0-a0 pwma- pwma[2] acifb- acbp[0] usart0- clk cat- csa[3] 4 6 pa03 3 vddio normal i/o usart0- cts spi- npcs[1] usart2- txd tc0-b0 pwma- pwma[3] acifb- acbn[3] usart0- clk cat- csb[3] 28 38 pa04 4 vddio normal i/o spi-miso twims0- twck usart1- rxd tc0-b1 pwma- pwma[4] acifb- acbp[1] cat- csa[7] 12 16 pa05 5 vddio normal i/o (twi) spi-mosi twims1- twck usart1- txd tc0-a1 pwma- pwma[5] acifb- acbn[0] twims0- twd cat- csb[7] 10 14 pa06 6 vddio high- drive i/o, 5v tolerant spi-sck usart2- txd usart1- clk tc0-b0 pwma- pwma[6] eic- extint[2] scif- gclk[1] cat- csb[1] 19 pa07 7 vddio normal i/o (twi) spi- npcs[0] usart2- rxd twims1- twalm twims0- twck pwma- pwma[7] acifb- acan[0] eic- nmi (extint[0]) cat- csb[2] 3 3 pa08 8 vddio high- drive i/o usart1- txd spi- npcs[2] tc0-a2 adcifb- adp[0] pwma- pwma[8] cat- csa[4] 2 2 pa09 9 vddio high- drive i/o usart1- rxd spi- npcs[3] tc0-b2 adcifb- adp[1] pwma- pwma[9] scif- gclk[2] eic- extint[1] cat- csb[4] 46 62 pa10 10 vddio normal i/o twims0- twd tc0-a0 pwma- pwma[10] acifb- acap[1] scif- gclk[2] cat- csa[5] 27 35 pa11 11 vddin normal i/o pwma- pwma[11] 47 63 pa12 12 vddio normal i/o usart2- clk tc0-clk1 cat-smp pwma- pwma[12] acifb- acan[1] scif- gclk[3] cat- csb[5] 26 34 pa13 13 vddin normal i/o gloc- out[0] gloc- in[7] tc0-a0 scif- gclk[2] pwma- pwma[13] cat-smp eic- extint[2] cat- csa[0] 36 48 pa14 14 vddio normal i/o adcifb- ad[0] tc0-clk2 usart2- rts cat-smp pwma- pwma[14] scif- gclk[4] cat- csa[6] 37 49 pa15 15 vddio normal i/o adcifb- ad[1] tc0-clk1 gloc- in[6] pwma- pwma[15] cat- sync eic- extint[3] cat- csb[6] 38 50 pa16 16 vddio normal i/o adcifb- ad[2] tc0-clk0 gloc- in[5] pwma- pwma[16] acifb- acrefn eic- extint[4] cat- csa[8]
11 32142ds?06/2013 atuc64/128/256l3/4u 39 51 pa17 17 vddio normal i/o (twi) tc0-a1 usart2- cts twims1- twd pwma- pwma[17] cat-smp cat-dis cat- csb[8] 41 53 pa18 18 vddio normal i/o adcifb- ad[4] tc0-b1 gloc- in[4] pwma- pwma[18] cat- sync eic- extint[5] cat- csb[0] 40 52 pa19 19 vddio normal i/o adcifb- ad[5] tc0-a2 twims1- twalm pwma- pwma[19] scif- gclk_in[ 0] cat-sync cat- csa[10] 25 33 pa20 20 vddin normal i/o usart2- txd tc0-a1 gloc- in[3] pwma- pwma[20] scif- rc32out cat- csa[12] 24 32 pa21 21 vddin normal i/o (twi, 5v tolerant, smbus) usart2- rxd twims0- twd tc0-b1 adcifb- trigger pwma- pwma[21] pwma- pwmaod [21] scif- gclk[0] cat- smp 9 13 pa22 22 vddio normal i/o usart0- cts usart2- clk tc0-b2 cat-smp pwma- pwma[22] acifb- acbn[2] cat- csb[10] 6 8 pb00 32 vddio normal i/o usart3- txd adcifb- adp[0] spi- npcs[0] tc0-a1 pwma- pwma[23] acifb- acap[2] tc1-a0 cat- csa[9] 20 pb01 33 vddio high- drive i/o usart3- rxd adcifb- adp[1] spi-sck tc0-b1 pwma- pwma[24] tc1-a1 cat- csb[9] 7 9 pb02 34 vddio normal i/o usart3- rts usart3- clk spi-miso tc0-a2 pwma- pwma[25] acifb- acan[2] scif- gclk[1] cat- csb[11] 8 10 pb03 35 vddio normal i/o usart3- cts usart3- clk spi-mosi tc0-b2 pwma- pwma[26] acifb- acbp[2] tc1-a2 cat- csa[11] 21 29 pb04 36 vddin normal i/o (twi, 5v tolerant, smbus) tc1-a0 usart1- rts usart1- clk twims0- twalm pwma- pwma[27] pwma- pwmaod [27] twims1- twck cat- csa[14] 20 28 pb05 37 vddin normal i/o (twi, 5v tolerant, smbus) tc1-b0 usart1- cts usart1- clk twims0- twck pwma- pwma[28] pwma- pwmaod [28] scif- gclk[3] cat- csb[14] 30 42 pb06 38 vddio normal i/o tc1-a1 usart3- txd adcifb- ad[6] gloc- in[2] pwma- pwma[29] acifb- acan[3] eic- nmi (extint[0]) cat- csb[13] 31 43 pb07 39 vddio normal i/o tc1-b1 usart3- rxd adcifb- ad[7] gloc- in[1] pwma- pwma[30] acifb- acap[3] eic- extint[1] cat- csa[13] 32 44 pb08 40 vddio normal i/o tc1-a2 usart3- rts adcifb- ad[8] gloc- in[0] pwma- pwma[31] cat- sync eic- extint[2] cat- csb[12] 29 39 pb09 41 vddio normal i/o tc1-b2 usart3- cts usart3- clk pwma- pwma[32] acifb- acbn[1] eic- extint[3] cat- csb[15] 23 31 pb10 42 vddin normal i/o tc1-clk0 usart1- txd usart3- clk gloc- out[1] pwma- pwma[33] scif- gclk_in[ 1] eic- extint[4] cat- csb[16] 44 56 pb11 43 vddio normal i/o tc1-clk1 usart1- rxd adcifb- trigger pwma- pwma[34] cat- vdiven eic- extint[5] cat- csa[16] 5 7 pb12 44 vddio normal i/o tc1-clk2 twims1- twalm cat- sync pwma- pwma[35] acifb- acbp[3] scif- gclk[4] cat- csa[15] 15 22 pb13 45 vddin usb i/o usbc-dm usart3- txd tc1-a1 pwma- pwma[7] adcifb- adp[1] scif- gclk[5] cat- csb[2] 16 23 pb14 46 vddin usb i/o usbc-dp usart3- rxd tc1-b1 pwma- pwma[24] scif- gclk[5] cat- csb[9] table 3-1. gpio controller func tion multiplexing
12 32142ds?06/2013 atuc64/128/256l3/4u 3.2 see section 3.3 for a description of the various peripheral signals. refer to ?electrical characteristics? on page 991 for a description of the electrical properties of the pin types used. 3.2.1 twi, 5v tolerant, and smbus pins some normal i/o pins offer twi, 5v tolerance, and smbus features. these features are only available when either of the twi functions or the pwmaod function in the pwma are selected for these pins. refer to the ?electrical characteristics? on page 991 for a description of the electrical properties of the twi, 5v tolerance, and smbus pins. 57 pb15 47 vddio high- drive i/o abdacb- clk iisc- imck spi-sck tc0-clk2 pwma- pwma[8] scif- gclk[3] cat- csb[4] 58 pb16 48 vddio normal i/o abdacb- dac[0] iisc-isck usart0- txd pwma- pwma[9] scif- gclk[2] cat- csa[5] 59 pb17 49 vddio normal i/o abdacb- dac[1] iisc-iws usart0- rxd pwma- pwma[10] cat- csb[5] 60 pb18 50 vddio normal i/o abdacb- dacn[0] iisc-isdi usart0- rts pwma- pwma[12] cat- csa[0] 4 pb19 51 vddio normal i/o abdacb- dacn[1] iisc-isdo usart0- cts pwma- pwma[20] eic- extint[1] cat- csa[12] 5 pb20 52 vddio normal i/o twims1- twd usart2- rxd spi- npcs[1] tc0-a0 pwma- pwma[21] usart1- rts usart1- clk cat- csa[14] 40 pb21 53 vddio normal i/o twims1- twck usart2- txd spi- npcs[2] tc0-b0 pwma- pwma[28] usart1- cts usart1- clk cat- csb[14] 41 pb22 54 vddio normal i/o twims1- twalm spi- npcs[3] tc0-clk0 pwma- pwma[27] adcifb- trigger scif- gclk[0] cat- csa[8] 54 pb23 55 vddio normal i/o spi-miso usart2- rts usart2- clk tc0-a2 pwma- pwma[0] cat-smp scif- gclk[6] cat- csa[4] 55 pb24 56 vddio normal i/o spi-mosi usart2- cts usart2- clk tc0-b2 pwma- pwma[1] adcifb- adp[1] scif- gclk[7] cat- csa[2] 61 pb25 57 vddio normal i/o spi- npcs[0] usart1- rxd tc0-a1 pwma- pwma[2] scif- gclk_in[ 2] scif- gclk[8] cat- csa[3] 21 pb26 58 vddio normal i/o spi-sck usart1- txd tc0-b1 pwma- pwma[3] adcifb- adp[0] scif- gclk[9] cat- csb[3] 24 pb27 59 vddin normal i/o usart1- rxd tc0-clk1 pwma- pwma[4] adcifb- adp[1] eic- nmi (extint[0]) cat- csa[9] table 3-1. gpio controller func tion multiplexing
13 32142ds?06/2013 atuc64/128/256l3/4u 3.2.2 peripheral functions each gpio line can be assigned to one of several peripheral functions. the following table describes how the various peripheral functions are selected. the last listed function has priority in case multiple functions are enabled on the same pin. 3.2.3 jtag port connections if the jtag is enabled, the jtag will take control over a number of pins, irrespectively of the i/o controller configuration. 3.2.4 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the i/o controller configurat ion. two different ocd trace pin mappings are possible, depending on the configuration of the ocd axs register. for details, see the avr32 uc technical reference manual . table 3-2. peripheral functions function description gpio controller function multiplexing gpio and gpio peripheral selection a to h nexus ocd aux port connections ocd trace system awire dataout awire output in two-pin mode jtag port connections jtag debug port oscillators osc0, osc32 table 3-3. jtag pinout 48-pin 64-pin pin name jtag pin 11 15 pa00 tck 14 18 pa01 tms 13 17 pa02 tdo 46pa03tdi table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 evti_n pa05 pb08 mdo[5] pa10 pb00 mdo[4] pa18 pb04 mdo[3] pa17 pb05 mdo[2] pa16 pb03 mdo[1] pa15 pb02 mdo[0] pa14 pb09
14 32142ds?06/2013 atuc64/128/256l3/4u 3.2.5 oscillator pinout the oscillators are not mapped to the normal gp io functions and their muxings are controlled by registers in the system control interface (scif). please refer to the scif chapter for more information about this. 3.2.6 other functions the functions listed in table 3-6 are not mapped to the normal gpio functions. the awire data pin will only be active after the awire is e nabled. the awire dataout pin will only be active after the awire is enabled an d the 2_pin_mode command has been sent. the wake_n pin is always enabled. please refer to section 6.1.4.2 on page 45 for constraints on the wake_n pin. evto_n pa04 pa04 mcko pa06 pb01 mseo[1] pa07 pb11 mseo[0] pa11 pb12 table 3-4. nexus ocd aux po rt connections pin axs=1 axs=0 table 3-5. oscillator pinout 48-pin 64-pin pin name oscillator pin 33pa08xin0 46 62 pa10 xin32 26 34 pa13 xin32_2 22pa09xout0 47 63 pa12 xout32 25 33 pa20 xout32_2 table 3-6. other functions 48-pin 64-pin pin name function 27 35 pa11 wake_n 22 30 reset_n awire data 11 15 pa00 awire dataout
15 32142ds?06/2013 atuc64/128/256l3/4u 3.3 signal descriptions the following table gives details on signal name classified by peripheral. table 3-7. signal descriptions list signal name function type active level comments audio bitstream dac - abdacb clk d/a clock out output dac1 - dac0 d/a bitstream out output dacn1 - dacn0 d/a inverted bitstream out output analog comparator interface - acifb acan3 - acan0 negative inputs for comparators "a" analog acap3 - acap0 positive inputs for comparators "a" analog acbn3 - acbn0 negative inputs for comparators "b" analog acbp3 - acbp0 positive inputs for comparators "b" analog acrefn common negative reference analog adc interface - adcifb ad8 - ad0 analog signal analog adp1 - adp0 drive pin for resistive touch screen output trigger external trigger input awire - aw data awire data i/o dataout awire data output for 2-pin mode i/o capacitive touch module - cat csa16 - csa0 capacitive sense a i/o csb16 - csb0 capacitive sense b i/o dis discharge current control analog smp smp signal output sync synchronize signal input vdiven voltage divider enable output external interrup t controller - eic nmi (extint0) non-maskable interrupt input extint5 - extint1 exte rnal interrupt input glue logic controller - gloc in7 - in0 inputs to lookup tables input out1 - out0 outputs from lookup tables output inter-ic sound (i2s) controller - iisc
16 32142ds?06/2013 atuc64/128/256l3/4u imck i2s master clock output isck i2s serial clock i/o isdi i2s serial data in input isdo i2s serial data out output iws i2s word select i/o jtag module - jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input power manager - pm reset_n reset input low pulse width modulation controller - pwma pwma35 - pwma0 pwma channel waveforms output pwmaod35 - pwmaod0 pwma channel waveforms, open drain mode output not all channels support open drain mode system control interface - scif gclk9 - gclk0 generic clock output output gclk_in2 - gclk_in0 generic clock input input rc32out rc32k output at startup output xin0 crystal 0 input analog/ digital xin32 crystal 32 inpu t (primary location) analog/ digital xin32_2 crystal 32 input (secondary location) analog/ digital xout0 crystal 0 output analog xout32 crystal 32 output (primary location) analog xout32_2 crystal 32 output (secondary location) analog serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o npcs3 - npcs0 spi peripheral chip select i/o low sck clock i/o timer/counter - tc0, tc1 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o table 3-7. signal descriptions list
17 32142ds?06/2013 atuc64/128/256l3/4u note: 1. adcifb: ad3 does not exist. b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twims0, twims1 twalm smbus smbalert i/o low twck two-wire serial clock i/o twd two-wire serial data i/o universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input low rts request to send output low rxd receive data input txd transmit data output table 3-7. signal descriptions list table 3-8. signal description list, continued signal name function type active level comments power vddcore core power supply / voltage regulator output power input/output 1.62v to 1.98v vddio i/o power supply power input 1.62v to 3.6v. vddio should always be equal to or lower than vddin. vddana analog power supply power input 1.62v to 1.98v advrefp analog reference voltage power input 1.62v to 1.98v vddin voltage regulator input power input 1.62v to 3.6v (1) gndana analog ground ground gnd ground ground auxiliary port - aux mcko trace data output clock output mdo5 - mdo0 trace data output output
18 32142ds?06/2013 atuc64/128/256l3/4u note: 1. see section 6. on page 40 3.4 i/o line considerations 3.4.1 jtag pins the jtag is enabled if tck is low while the reset_n pin is re leased. the tck, tms, and tdi pins have pull-up resistors when jtag is enabled. the tck pin always has pull-up enabled dur- ing reset. the tdo pin is an output, driven at vddio, and has no pull-up resistor. the jtag pins can be used as gpio pins and multiplex ed with peripherals when the jtag is disabled. please refer to section 3.2.3 on page 13 for the jtag port connections. 3.4.2 pa00 note that pa00 is multiplexed with tck. pa00 gpio function must only be used as output in the application. 3.4.3 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddin. as the product integrates a power-on reset detector, the reset_n pin can be left unconnected in case no reset from the system nee ds to be applied to the product. the reset_n pin is also used for the awire de bug protocol. when the pin is used for debug- ging, it must not be driven by external circuitry. 3.4.4 twi pins pa21/pb04/pb05 when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. when used as gpio pins or used for other peripherals, the pins have the same characteristics as other gpio pins. sele cted pins are also smbus compliant (refer to section on page 10 ). as required by the smbus specification, these pins provide no leakage path to ground when the atuc64/128/256l3/4u is powered down. this allows other devices on the smbus to continue communicating even though the atuc64/128/256l3/4u is not powered. after reset a twi function is selected on these pins instead of the gpio. please refer to the gpio module configuration chapter for details. mseo1 - mseo0 trace frame control output evti_n event in input low evto_n event out output low general purpose i/o pin pa22 - pa00 parallel i/o controller i/o port 0 i/o pb27 - pb00 parallel i/o controller i/o port 1 i/o table 3-8. signal description list, continued signal name function type active level comments
19 32142ds?06/2013 atuc64/128/256l3/4u 3.4.5 twi pins pa05/pa07/pa17 when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. when used as gpio pins or used for other peripherals, the pins have the same characteristics as other gpio pins. after reset a twi function is selected on these pins instead of the gpio. please refer to the gpio module configuration chapter for details. 3.4.6 gpio pins all the i/o lines integrate a pull-up resistor ? programming of this pull-up resistor is performed independently for each i/o line through the gpio controllers. after reset, i/o lines default as inputs with pull-up resistors disabled, except pa00 which has the pull-up resistor enabled. pa20 selects scif-rc32out (gpio function f) as default enabled after reset. 3.4.7 high-drive pins the six pins pa02, pa06, pa08, pa09, pb01, and pb15 have high-drive output capabilities. refer to section 34. on page 991 for electrical characteristics. 3.4.8 usb pins pb13/pb14 when these pins are used for usb, the pins ar e behaving according to the usb specification. when used as gpio pins or used for other per ipherals, the pins have the same behaviour as other normal i/o pins, but the characteristics are different. refer to section 34. on page 991 for electrical characteristics. to be able to use the usb i/o the vddin power supply must be 3.3 v nominal. 3.4.9 rc32out pin 3.4.9.1 clock output at startup after power-up, the clock generated by the 32khz rc oscillator (rc32k) will be output on pa20, even when the device is still reset by the powe r-on reset circuitry. this clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply volt- age up to an acceptable value. the clock will be available on pa20, but will be di sabled if one of the following conditions are true: ? pa20 is configured to use a gpio function other than f (scif-rc32out) ? pa20 is configured as a general purpose input/output (gpio) ? the bit frc32 in the power manager ppcr register is written to zero (refer to the power manager chapter) the maximum amplitude of the clock signal will be defined by vddin. once the rc32k output on pa20 is disabled it can never be enabled again. 3.4.9.2 xout32_2 function pa20 selects rc32out as default enabled after reset. this function is not automatically dis- abled when the user enables the xout32_2 function on pa20. this disturbs the oscillator and may result in the wrong frequency. to avoid this, rc32out must be disabled when xout32_2 is enabled.
20 32142ds?06/2013 atuc64/128/256l3/4u 3.4.10 adc input pins these pins are regular i/o pins powered from the vddio. however, when these pins are used for adc inputs, the voltage applied to the pin must not exceed 1.98v. internal circuitry ensures that the pin cannot be used as an analog input pin when the i/o drives to vdd. when the pins are not used for adc inputs, the pins may be driven to the full i/o voltage range.
21 32142ds?06/2013 atuc64/128/256l3/4u 4. mechanical characteristics 4.1 thermal considerations 4.1.1 thermal data table 4-1 summarizes the thermal resistance data depending on the package. 4.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 4-1 . ? ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 4-1 . ? ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in section 34.4 on page 992 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 4-1. thermal resistance data symbol parameter condition package typ unit ? ja junction-to-ambient thermal resistance still air tqfp48 54.4 ? c/w ? jc junction-to-case thermal resistance tqfp48 15.7 ? ja junction-to-ambient thermal resistance still air qfn48 26.0 ? c/w ? jc junction-to-case thermal resistance qfn48 1.6 ? ja junction-to-ambient thermal resistance still air tllga48 25.4 ? c/w ? jc junction-to-case thermal resistance tllga48 12.7 ? ja junction-to-ambient thermal resistance still air tqfp64 52.9 ? c/w ? jc junction-to-case thermal resistance tqfp64 15.5 ? ja junction-to-ambient thermal resistance still air qfn64 22.9 ? c/w ? jc junction-to-case thermal resistance qfn64 1.6 t j t a p d ? ja ? ?? + = t j t a p ? d ? ? heatsink ?? jc ?? ++ =
22 32142ds?06/2013 atuc64/128/256l3/4u 4.2 package drawings figure 4-1. tqfp-48 package drawing table 4-2. device and package maximum weight 140 mg table 4-3. package characteristics moisture sensitivity level msl3 table 4-4. package reference jedec drawing reference ms-026 jesd97 classification e3
23 32142ds?06/2013 atuc64/128/256l3/4u figure 4-2. qfn-48 package drawing note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 4-5. device and package maximum weight 140 mg table 4-6. package characteristics moisture sensitivity level msl3 table 4-7. package reference jedec drawing reference m0-220 jesd97 classification e3
24 32142ds?06/2013 atuc64/128/256l3/4u figure 4-3. tllga-48 package drawing table 4-8. device and package maximum weight 39.3 mg table 4-9. package characteristics moisture sensitivity level msl3 table 4-10. package reference jedec drawing reference n/a jesd97 classification e4
25 32142ds?06/2013 atuc64/128/256l3/4u figure 4-4. tqfp-64 package drawing table 4-11. device and package maximum weight 300 mg table 4-12. package characteristics moisture sensitivity level msl3 table 4-13. package reference jedec drawing reference ms-026 jesd97 classification e3
26 32142ds?06/2013 atuc64/128/256l3/4u figure 4-5. qfn-64 package drawing note: the exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliabil ity. table 4-14. device and package maximum weight 200 mg table 4-15. package characteristics moisture sensitivity level msl3 table 4-16. package reference jedec drawing reference m0-220 jesd97 classification e3
27 32142ds?06/2013 atuc64/128/256l3/4u 4.3 soldering profile table 4-17 gives the recommended soldering profile from j-std-20. a maximum of three reflow passes is allowed per component. table 4-17. soldering profile profile feature green package average ramp-up rate (217c to peak) 3c/s max preheat temperature 175c 25c 150-200c time maintained above 217c 60-150 s time within 5 ? c of actual peak temperature 30 s peak temperature range 260c ramp-down rate 6c/s max time 25 ? c to peak temperature 8 minutes max
28 32142ds?06/2013 atuc64/128/256l3/4u 5. ordering information table 5-1. ordering information device ordering code carrier type package package type temperature operating range atuc256l3u atuc256l3u-autes es tqfp 64 jesd97 classification e3 n/a atuc256l3u-aut tray industrial (-40 ? c to 85 ? c) atuc256l3u-aur tape & reel atuc256l3u-z3utes es qfn 64 n/a atuc256l3u-z3ut tray industrial (-40 ? c to 85 ? c) atuc256l3u-z3ur tape & reel atuc128l3u atuc128l3u-aut tray tqfp 64 jesd97 classification e3 industrial (-40 ? c to 85 ? c) atuc128l3u-aur tape & reel atuc128l3u-z3ut tray qfn 64 atuc128l3u-z3ur tape & reel atuc64l3u atuc64l3u-aut tray tqfp 64 jesd97 classification e3 industrial (-40 ? c to 85 ? c) atuc64l3u-aur tape & reel atuc64l3u-z3ut tray qfn 64 atuc64l3u-z3ur tape & reel
29 32142ds?06/2013 atuc64/128/256l3/4u atuc256l4u atuc256l4u-autes es tqfp 48 jesd97 classification e3 n/a atuc256l4u-aut tray industrial (-40 ? c to 85 ? c) atuc256l4u-aur tape & reel atuc256l4u-zautes es qfn 48 n/a atuc256l4u-zaut tray industrial (-40 ? c to 85 ? c) atuc256l4u-zaur tape & reel atuc256l4u-d3hes es tllga 48 jesd97 classification e4 n/a atuc256l4u-d3ht tray industrial (-40 ? c to 85 ? c) atuc256l4u-d3hr tape & reel atuc128l4u atuc128l4u-aut tray tqfp 48 jesd97 classification e3 atuc128l4u-aur tape & reel atuc128l4u-zaut tray qfn 48 atuc128l4u-zaur tape & reel atuc128l4u-d3ht tray tllga 48 jesd97 classification e4 atuc128l4u-d3hr tape & reel atuc64l4u atuc64l4u-aut tray tqfp 48 jesd97 classification e3 atuc64l4u-aur tape & reel atuc64l4u-zaut tray qfn 48 atuc64l4u-zaur tape & reel atuc64l4u-d3ht tray tllga 48 jesd97 classification e4 atuc64l4u-d3hr tape & reel table 5-1. ordering information device ordering code carrier type package package type temperature operating range
30 32142ds?06/2013 atuc64/128/256l3/4u 6. errata 6.1 rev. c 6.1.1 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 3. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround none. 6.1.2 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst).
31 32142ds?06/2013 atuc64/128/256l3/4u 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr. 6.1.3 twi 1. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 2. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 6.1.4 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 6.1.5 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph-
32 32142ds?06/2013 atuc64/128/256l3/4u eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register. 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 6.1.6 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 6.1.7 flash 1. corrupted data in flash may happen after flash page write operations after a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. this may lead to an exception or to others errors derived from this corrupted read access. fix/workaround before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xffff_ffff content at any address in the page. 6.2 rev. b 6.2.1 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one f sab 7 f aw cv 3 ? ---------------- - =
33 32142ds?06/2013 atuc64/128/256l3/4u - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 3. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround none. 6.2.2 wdt 1. wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value. 6.2.3 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst).
34 32142ds?06/2013 atuc64/128/256l3/4u 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr. 6.2.4 twi 1. twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. 2. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 3. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 6.2.5 pwma 1. the sr.ready bit cannot be cleared by writing to scr.ready the ready bit in the status register will not be cleared when writing a one to the corre- sponding bit in the status clear register. th e ready bit will be cleared when the busy bit is set. fix/workaround
35 32142ds?06/2013 atuc64/128/256l3/4u disable the ready interrupt in the interrupt handler when receiving the interrupt. when an operation that triggers the busy/ready bit is started, wait until the ready bit is low in the sta- tus register before enabling the interrupt. 6.2.6 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped. fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 6.2.7 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph- eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register. 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 3. cat consumes unnecessary power when disabled or when autonomous touch not used a cat prescaler controlled by the atcfg0.div field will be active even when the cat mod- ule is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. fix/workaround if the cat module is not used, disable the clk_cat clock in the pm module. if the cat module is used but the autonomous touch feature is not used, the power consumption of the cat module may be reduced by writing 0xffff to the atcfg0.div field. 6.2.8 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround
36 32142ds?06/2013 atuc64/128/256l3/4u issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 6.2.9 flash 1. corrupted data in flash may happen after flash page write operations after a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. this may lead to an exception or to others errors derived from this corrupted read access. fix/workaround before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xffff_ffff content at any address in the page. 6.3 rev. a 6.3.1 device 1. jtagid is wrong the jtagid reads 0x021df03f for all devices. fix/workaround none. 6.3.2 flashcdw 1. general-purpose fuse programming does not work the general-purpose fuses cannot be programmed and are stuck at 1. please refer to the fuse settings chapter in the flashcdw for more information about what functions are affected. fix/workaround none. 2. set security bit command does not work the set security bit (ssb) command of the flas hcdw does not work . the device cannot be locked from external jtag, awire, or other debug accesses. fix/workaround none. 3. flash programming time is longer than specified f sab 7 f aw cv 3 ? ---------------- - =
37 32142ds?06/2013 atuc64/128/256l3/4u the flash programming time is now : fix/workaround none. 4. power manager 5. clock failure detector (cfd) can be issued while turning off the cfd while turning off the cfd, the cfd bit in the status register (sr) can be set. this will change the main cl ock source to rcsys. fix/workaround solution 1: enable cfd in terrupt. if cfd interrupt is issues after turning off the cfd, switch back to original main clock source. solution 2: only turn off the cfd while running the main clock on rcsys. 6. sleepwalking in idle and frozen sleep mode will mask all other pb clocks if the cpu is in idle or frozen sleep mode and a module is in a state that triggers sleep walk- ing, all pb clocks will be masked except the pb clock to the sleepwalking module. fix/workaround mask all clock requests in the pm.ppcr register before going into idle or frozen mode. 2. unused pb clocks are running three unused pba clocks are en abled by default and will cause increased active power consumption. fix/workaround disable the clocks by writing zeroes to bits [27: 25] in the pba clock mask register. 6.3.3 scif 1. the rc32k output on pa20 is not always permanently disabled the rc32k output on pa20 may sometimes re-appear. fix/workaround before using rc32k for other purposes, the following procedure has to be followed in order to properly disable it: - run the cpu on rcsys - disable the output to pa20 by writing a zero to pm.ppcr.rc32out - enable rc32k by writing a one to scif.rc 32kcr.en, and wait for this bit to be read as one - disable rc32k by writing a ze ro to scif.rc32kcr.en, and wait for this bit to be read as zero. 2. pll lock might not clear after disable table 6-1. flash characteristics symbol parameter conditions min typ max unit t fpp page programming time f clk_hsb = 50mhz 7.5 ms t fpe page erase time 7.5 t ffp fuse programming time 1 t fea full chip erase time (ea) 9 t fce jtag chip erase time (chip_erase) f clk_hsb = 115khz 250
38 32142ds?06/2013 atuc64/128/256l3/4u under certain circumstances, the lock signal from the phase locked loop (pll) oscillator may not go back to zero after th e pll oscillator has been disabl ed. this can cause the prop- agation of clock signals with the wrong frequency to parts of the system that use the pll clock. fix/workaround pll must be turned off befor e entering stop, deepstop or static sleep modes. if pll has been turned off, a delay of 30us must be observed after the pll has been enabled again before the scif.pll0lock bit can be used as a valid indication that the pll is locked. 3. pllcount value larger than zero can cause pllen glitch initializing the pllcount with a value greater than zero creates a glitch on the pllen sig- nal during asynchronous wake up. fix/workaround the lock-masking mechanism for the pll should not be used. the pllcount field of the pll control register should always be written to zero. 4. rcsys is not calibrated the rcsys is not calibrated and will run faster than 115.2khz. fre quencies around 150khz can be expected. fix/workaround if a known clock source is available the rc sys can be runtime calibrated by using the fre- quency meter (freqm) and tuning the rcsys by writing to the rccr register in scif. 5. writing 0x5a5a5a5a to the scif memory range will enable the scif unlock feature the scif unlock feature will be enabled if the val ue 0x5a5a5a5a is written to any loca- tion in the scif memory range. fix/workaround none. 6.3.4 wdt 1. clearing the watchdog timer (wdt) counter in second half of timeout period will issue a watchdog reset if the wdt counter is cleared in the second half of the ti meout period, the wdt will immedi- ately issue a watchdog reset. fix/workaround use twice as long timeout period as needed and clear the wdt counter within the first half of the timeout period. if the wdt counter is cl eared after the first half of the timeout period, you will get a watchdog reset immediately. if the wdt counter is not clea red at all, the time before the reset will be tw ice as long as needed. 2. wdt control register does not have synchronization feedback when writing to the timeout pr escale select (psel), time ban prescale select (tban), enable (en), or wdt mode (mode) fieldss of the wdt control register (ctrl), a synchro- nizer is started to propagate the values to the wdt clcok domain. this synchronization takes a finite amount of time, but only the status of the synchronization of the en bit is reflected back to the user. writing to the synch ronized fields during synchronization can lead to undefined behavior. fix/workaround -when writing to the affected fields, the user must ensure a wait corresponding to 2 clock cycles of both the wdt peripheral bus clock and the selected wdt clock source. -when doing writes that changes the en bit, the en bit can be read back until it reflects the written value.
39 32142ds?06/2013 atuc64/128/256l3/4u 6.3.5 gpio 1. clearing interrupt flags can mask other interrupts when clearing interrupt flags in a gpio port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. fix/workaround read the pvr register of the port before and af ter clearing the interrupt to see if any pin change has happened while clearing the interr upt. if any change occurred in the pvr between the reads, they must be treated as an interrupt. 6.3.6 spi 1. spi data transfer hangs with csr0.csaat==1 and mr.modfdis==0 when csr0.csaat==1 and mode fault detection is enabled (mr.modfdis==0), the spi module will not start a data transfer. fix/workaround disable mode fault detection by writing a one to mr.modfdis. 2. disabling spi has no effect on the sr.tdre bit disabling spi has no effect on the sr.tdre bit whereas the write data command is filtered when spi is disabled. writing to tdr when spi is disabled will not clear sr.tdre. if spi is disabled during a pdca transfer, the pdca will continue to write data to tdr until its buffer is empty, and this data will be lost. fix/workaround disable the pdca, add two nops, and disable the spi. to continue the transfer, enable the spi and pdca. 3. spi disable does not work in slave mode spi disable does not work in slave mode. fix/workaround read the last received data, then perform a software reset by writing a one to the software reset bit in the control register (cr.swrst). 4. spi bad serial clock generation on 2nd chip_select when scbr=1, cpol=1, and ncpha=0 when multiple chip selects (cs) are in use, if one of the baudrates equal 1 while one (csrn.scbr=1) of the others do not equal 1, and csrn.cpol=1 and csrn.ncpha=0, then an additional pulse will be genera ted on sck. fix/workaround when multiple cs are in use, if one of the baudrates equals 1, the others must also equal 1 if csrn.cpol=1 and csrn.ncpha=0. 5. spi mode fault detection enable causes incorrect behavior when mode fault detection is enabled (mr. modfdis==0), the spi module may not operate properly. fix/workaround always disable mode fault detection before using the spi by writing a one to mr.modfdis. 6. spi rdr.pcs is not correct the pcs (peripheral chip select) field in th e spi rdr (receive data register) does not correctly indicate the value on the npcs pins at the end of a transfer. fix/workaround do not use the pcs field of the spi rdr.
40 32142ds?06/2013 atuc64/128/256l3/4u 6.3.7 twi 1. twis may not wake the device from sleep mode if the cpu is put to a sleep mode (except idle and frozen) directly after a twi start condi- tion, the cpu may not wake upon a twis address match. the request is nacked. fix/workaround when using the twi address match to wake t he device from sleep, do not switch to sleep modes deeper than frozen. another solution is to enable asynchronous eic wake on the twis clock (twck) or twis data (twd) pi ns, in order to wake the system up on bus events. 2. smbalert bit may be set after reset the smbus alert (smbalert) bit in the status register (sr) might be erroneously set after system reset. fix/workaround after system reset, clear the sr.smbalert bit before commencing any twi transfer. 3. clearing the nak bit before the btf bit is set locks up the twi bus when the twis is in transmit mode, clearing the nak received (nak) bit of the status reg- ister (sr) before the end of the acknowl edge/not acknowledge cycle will cause the twis to attempt to continue transmitting data, thus locking up the bus. fix/workaround clear sr.nak only after the byte transfer finished (btf) bit of the same register has been set. 4. twis stretch on address match error when the twis stretches twck due to a slave address match, it also holds twd low for the same duration if it is to be receiving data. when twis releases twck, it releases twd at the same time. this can cause a twi timing violation. fix/workaround none. 5. twim twalm polarity is wrong the twalm signal in the twim is active high instead of active low. fix/workaround use an external inverter to invert the signal going into the twim. when using both twim and twis on the same pins, the twalm cannot be used. 6.3.8 pwma 1. the sr.ready bit cannot be cleared by writing to scr.ready the ready bit in the status register will not be cleared when writing a one to the corre- sponding bit in the status clear register. th e ready bit will be cleared when the busy bit is set. fix/workaround disable the ready interrupt in the interrupt handler when receiving the interrupt. when an operation that triggers the busy/ready bit is started, wait until the ready bit is low in the sta- tus register before enabling the interrupt. 6.3.9 tc 1. channel chaining skips first pulse for upper channel when chaining two channels using the block mode register, the first pulse of the clock between the channels is skipped.
41 32142ds?06/2013 atuc64/128/256l3/4u fix/workaround configure the lower channel with ra = 0x1 and rc = 0x2 to produce a dummy clock cycle for the upper channel. after the dummy cycle has been generated, indicated by the sr.cpcs bit, reconfigure the ra and rc registers for the lower channel with the real values. 6.3.10 adcifb 1. adcifb dma transfer does not work with divided pba clock dma requests from the adcifb will not be performed when the pba clock is slower than the hsb clock. fix/workaround do not use divided pba clock when th e pdca transfers from the adcifb. 6.3.11 cat 1. cat qmatrix sense capacitors discharged prematurely at the end of a qmatrix burst charging sequence that uses different burst count values for different y lines, the y lines may be incorrectly grounded for up to n-1 periods of the periph- eral bus clock, where n is the ratio of t he pb clock frequency to the gclk_cat frequency. this results in premature loss of charge from the sense capacitors and thus increased vari- ability of the acquir ed count values. fix/workaround enable the 1kohm drive resistors on all implemented qmatrix y lines (csa 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the csares register. 2. autonomous cat acquisition must be longer than ast source clock period when using the ast to trigger cat autonomous touch acquisition in sleep modes where the cat bus clock is turned off, the cat will start several acquisitions if the period of the ast source clock is larger than one cat acquisition. one ast clock period after the ast trigger, the cat clock will automatically stop and t he cat acquisition can be stopped prematurely, ruining the result. fix/workaround always ensure that the atcfg1.max field is set so that the duration of the autonomous touch acquisition is greater than one clock period of the ast source clock. 3. cat consumes unnecessary power when disabled or when autonomous touch not used a cat prescaler controlled by the atcfg0.div field will be active even when the cat mod- ule is disabled or when the autonomous touch feature is not used, thereby causing unnecessary power consumption. fix/workaround if the cat module is not used, disable the clk_cat clock in the pm module. if the cat module is used but the autonomous touch feature is not used, the power consumption of the cat module may be reduced by writing 0xffff to the atcfg0.div field. 4. cat module does not terminate qtouch burst on detect the cat module does not terminate a qtouch burst when the detection voltage is reached on the sense capacitor. this can ca use the sense capacitor to be charged more than necessary. depending on the dielectric abso rption characteristics of the capacitor, this can lead to unstable measurements. fix/workaround use the minimum possible value for the max field in the atcfg1, tg0cfg1, and tg1cfg1 registers.
42 32142ds?06/2013 atuc64/128/256l3/4u 6.3.12 awire 1. awire memory_speed_request comm and does not return correct cv the awire memory_speed_request command does not retu rn a cv co rresponding to the formula in the awire debug interface chapter. fix/workaround issue a dummy read to address 0x100000000 before issuing the memory_speed_request command and use this formula instead: 6.3.13 flash 1. corrupted data in flash may happen after flash page write operations after a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. this may lead to an exception or to others errors derived from this corrupted read access. fix/workaround before any flash page write operation, each write in the page buffer must preceded by a write in the page buffer with 0xffff_ffff content at any address in the page. 6.3.14 i/o pins 1. pa05 is not 3.3v tolerant. pa05 should be grounded on the pcb and left unused if vddio is above 1.8v. fix/workaround none. 2. no pull-up on pins that are not bonded pb13 to pb27 are not bonded on uc3l0256/128, but has no pull-up and can cause current consumption on vddio/vddin if left undriven. fix/workaround enable pull-ups on pb13 to pb27 by writing 0x0fffe000 to the puers1 register in the gpio. 3. pa17 has low esd tolerance pa17 only tolerates 500v esd pulses (human body model). fix/workaround care must be taken during manufacturing and pcb design. f sab 7 f aw cv 3 ? ---------------- - =
43 32142ds?06/2013 atuc64/128/256l3/4u 7. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 7.1 rev. d ? 06/2013 7.2 rev. c ? 01/2012 7.3 rev. b ? 12/2011 7.4 rev. a ? 12/2011 1. updated the datasheet with a ne w atmel blue logo and the last page. 2. added flash errata. 1. description: dfll frequency is 20 to 150mhz, not 40 to 150mhz. 2. block diagram: gclk_in is input, not outpu t. cat smp corrected from i/o to output. spi npcs corrected from output to i/o. 3, package and pinout: extint0 in signal descriptions table is nmi. 4, supply and startup considerations: in 1.8v si ngle supply mode figure, the input voltage is 1.62-1.98v, not 1.98-3.6v . ?on system start-up, the dfll is disabled? is replaced by ?on system start-up, all high-speed clocks are disabled?. 5, adcifb: prnd signal removed from block diagram. 6, electrical charateristics: added 64-pin package information to i/o pin characteristics tables and digital clock characteristics table. 7, mechanical characteristics: qfn48 package drawing updated. note that the package drawing for qfn48 is correct in datasheet rev a, but wrong in rev b. added notes to package drawings. 8. summary: removed programming and debugging chapter, added processor and architecture chapter. 1. jtag data registers subchapter added in the programming and debugging chapter, containing jtag ids. 1. initial revision.
i 32142ds?06/2013 atuc64/128/256l3/4u table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 3 2 overview ............ ................ ................ ............... .............. .............. ............ 5 2.1 block diagram ...................................................................................................5 2.2 configuration summary .....................................................................................6 3 package and pinout ................. ................ ................. ................ ............... 7 3.1 package .............................................................................................................7 3.2 see section 3.3 for a description of the various peripheral signals. ................12 3.3 signal descriptions ..........................................................................................15 3.4 i/o line considerations ...................................................................................18 4 mechanical characteristics ....... ................. ................ ................. .......... 21 4.1 thermal considerations ..................................................................................21 4.2 package drawings ...........................................................................................22 4.3 soldering profile ..............................................................................................27 5 ordering information .......... .............. ............... .............. .............. .......... 28 6 errata ............. ................ ................. ................ ................. .............. .......... 30 6.1 rev. c ..............................................................................................................30 6.2 rev. b ..............................................................................................................32 6.3 rev. a ..............................................................................................................36 7 datasheet revision history .... ................ ................. ................ ............. 43 7.1 rev. d ? 06/2013 .............................................................................................43 7.2 rev. c ? 01/2012 .............................................................................................43 7.3 rev. b ? 12/2011 .............................................................................................43 7.4 rev. a ? 12/2011 .............................................................................................43 table of contents.......... ................. ................ ................. ................ ........... i
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